Most code tells a computer what to do. VHDL tells a computer what to be. It is a language used to build actual, physical computer chips using code.
Reads line by line. Step one finishes, then step two starts. It takes time to move down the list.
Everything happens exactly at the same time. Wires don't wait in line. They work instantly.
Building a real, physical computer chip in a factory costs millions of dollars. If you make one mistake, the chip goes in the trash.
VHDL lets engineers simulate the chip. This means we build a fake, virtual version of the chip on our screen.
We can press fake buttons and watch fake lights turn on. If there is a mistake, we just change the code. It costs zero dollars to fix a mistake on a screen.
FPGA stands for Field Programmable Gate Array.
Think of it as a shape-shifting chip. You plug it into your computer, send your VHDL code to it, and the inside of the chip physically changes to match your code.
If you don't like it, you can erase it and turn it into a completely different chip tomorrow.
ASIC stands for Application-Specific Integrated Circuit.
This is a permanent chip. Once you test your VHDL code and know it is perfect, you send it to a giant factory.
They print your chip into solid silicon. It can never be changed. It is very fast, very cheap to make millions of them, but you cannot fix a bug later.
The Entity is the outside of the box. It only lists the pins. What goes in? What goes out? It does not know how the math works inside. It only knows the inputs and outputs.
The Architecture lives inside the box. This is where you write the rules. If button A and button B are pushed, turn on light C. This is the brain.
In normal coding, you have "variables" to store data. In VHDL, we use Signals.
A signal is literally a wire. When you write a rule that says Signal_X <= Signal_Y,
you are asking the computer to solder a wire from pin Y to pin X.
Sometimes you need to send a large number, like 255. A single wire can only send a 0 or a 1. To send bigger numbers, we tie wires together into bundles.
In VHDL, a bundle of wires is called a Vector.
-- 1. The Box (Inputs and Outputs)
entity LightSwitch is
port (
Switch1 : in bit;
Switch2 : in bit;
LightBulb : out bit
);
end LightSwitch;
-- 2. The Brains (The Rules)
architecture Rules of LightSwitch is
begin
-- The light only turns on if BOTH switches are ON
LightBulb <= Switch1 and Switch2;
end Rules;
You don't have to teach the computer how to add numbers or count. Smart engineers already did that. At the top of your file, you "check out" a library to use their tools.
-- Always put this at the top of your file:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Chips are incredibly fast. If you don't control them, data crashes into other data like cars at an intersection with no traffic lights. To fix this, we use a Clock Signal. It is a master wire that pulses ON and OFF millions of times a second. Rule: The chip is only allowed to take a step and do math when the clock ticks. This keeps the whole city moving in perfect rhythm.
Wires do not have memories. When you let go of a button, the wire instantly forgets it was ever pressed.
To remember things, we build a Flip-Flop. It is a tiny vault. When the clock ticks, the vault opens, grabs the data on the wire, and locks it inside. It holds that data safely until the next clock tick.
No clock. No memory. It happens instantly.
Example: If you press "A" and "B", the "C" light turns on right now. If you let go, it turns off right now.
Uses the clock. Has memory. It waits in line.
Example: Pressing a button changes a saved score, but the score only updates on the screen when the next clock tick happens.
We learned earlier that in VHDL, all code happens at the exact same time. But sometimes, humans need code to run in order (Step 1, then Step 2). We can do this using a Process.
A process is a special sandbox. Outside the sandbox, everything happens instantly. Inside the sandbox, the code is read from top to bottom, just like Python or C.
How does a traffic light know what to do next? It uses a "State Machine." It remembers what state it is currently in, and looks at rules to decide where to go next.
To test our chip, we don't buy physical buttons. We write a second VHDL file called a Testbench. It acts as a fake world around our chip. It generates fake button presses and fake clock ticks to see if our chip survives the test.
If you write an `If` rule but forget to write the `Else` rule, the computer panics. It doesn't know what to do.
To save itself, it secretly builds a vault (memory) to hold the old value. This is called a "Latch" and it will usually destroy your chip's timing and break your project. Always write an `Else`!
Type your VHDL into a text file. Define your boxes and your rules.
Run the virtual playground. Send fake inputs to make sure the math is correct.
A computer program translates your VHDL words into an actual map of tiny gates and wires.
The map is locked into an FPGA shape-shifter chip, or sent to a factory for a permanent ASIC.
When you hit "compile," it doesn't make a software app. It enters Synthesis.
The compiler looks at your code and physically connects tiny hardware blocks together. It routes wires across the silicon chip like drawing streets on a city map.
If your code is too big or too slow, the "streets" get too long, and data won't arrive before the clock ticks. This is called a timing failure.
VHDL is old, but it is deeply trusted. When a machine cannot afford to crash, engineers use VHDL. You will find VHDL hardware in:
Satellites run on pure hardware because space radiation crashes normal software.
A hospital life-support machine cannot afford to "freeze" or wait to load.
It processes millions of radio waves per second instantly, with zero delay.
The physical world is waiting for your code.